Although various forms of semiconductor memory devices with different formats have been proposed, all have sought to provide a device with minimum area requirements that operate with adequate speed. Double-rail MOSFET (Metal Oxide Silicon Field Effect Transistor) memory systems have previously been disclosed, but such systems are relatively complex and require dual bit lines and four or six transistors per cell. So-called single-rail MOSFET memory systems utilizing three transistor cells have also been devised, and in U.S. Pat. No. 3,533,089 a single-rail memory with a single transistor cell and capacitive storage is disclosed. While this latter arrangement provided some reduction in the area required for each bit over the prior three transistor cell, its area requirements were still substantial because each cell included not only the drain and gate of the active transistor element but also a fairly large source-capacitor element located adjacent to the transistor gate. Semiconductor memory devices inherently include a large array of cells on each chip. Thus, the total area required for the source-capacitor in the aforesaid prior art significantly increased the total area of memory devices using them. Since the cost of such devices is directly related to area, it therefore became highly desirable to reduce the area required for each cell to an absolute minimum without sacrificing necessary performance characteristics. The present invention provides a solution to this problem.